As the whole industry and technology have been rapidly grown in recent years, semiconductor integrated circuits have been remarkably developed in general fields including cellular phones, MP3, displays, etc. Also, the growth of surface mounter technology which directly loads small chip components and small-form-factor electronic products is getting faster and faster. Thus, soft circuit substrates are now used more often than hard ones for minimization and flexibility of products. Due to the recent importance of printing circuit substrate, metal clad laminates such as copper clad laminates are manufactured in various ways and used widely.
The usual method to fabricate metal clad laminates, which are industrial laminates of soft circuit substrates, is to laminate with insulating base film by applying various adhesives on the metal sheet. For instance, Japanese Laid-Open Patent Publication No. PYUNG 8-162734 (Jun. 21, 1996) discloses the manufacturing method of three-layered metal clad laminates using thermoplastic Polyimide as the adhesive. Yet, it has a disadvantage that the laminates become thicker and less flexible since the bonded layer is more than 10 μm and show poor performance at high temperature just as solder, because the glass transition temperature of the adhesive is lower than 300° C.
Another existing technology to fabricate two-layered metal clad laminates is to coat a polyamic acid type resin on metal sheets and heat-treat at higher than 300° C. to produce polyimide dielectric films. But, there are a few problems that a big quantity of moisture is lost during the heat treatment and the volume contracts, causing the whole substrates get bent and curled up and dropping the adhesive power between the metal and insulating layers.
Japanese Patent Publication No. 2003-509586 (Mar. 11, 2003) discloses a manufacturing method of metal clad laminates by depositing more than one kind of metals such as Ni, Cu, Ti, Mo, Cr, etc. on insulting polyimide film through sputtering to form primary interface and then fabricate metal clad laminates by electroplating. In this case, uncurled products can be obtained since there is no decrease in volume in polyimide layer and the thickness of metal layers can be controlled depending on the plating condition. Yet, the sputtering process before electroplating is performed in a vacuum, making continuous process hard, manufacturing slow, and price going high.
On the other hand, as the size of flat panel displays such as plasma display panel (PDP), liquid crystal display (LCD), organic and inorganic electro luminescent display (ELD), etc. is getting broader and high resolution and high quality are needed, the length of metal patterns on circuit substrates has been remarkably increased, and resistance and capacitance value of wiring have extremely increased, too. Accordingly, the operation speed of displays slows down and distortion appears. Due to such problems, the development of process and materials to form low-resistance metal patterns is regarded as essential technology.
The general method to fabricate metal patterns is metal deposition or sputtering or to spin coat the ink including metals and laminate metals, then form desirable patterns after the photo resist process through exposure and development and then indirectly produce them by etching. Yet, the above method has a few problems that it is a complicated process, an improper way to produce multi-layered patterns, and there is also limitation in development of vacuum deposition equipment for maximizing the size of substrates.
US patent No. 2006-0062978 discloses a method to directly fabricate a pattern by adhering a pattern-formed mask onto substrates such as silicon wafer and forming metals by sputtering, but this reduces fabrication ability due to long sputtering time to satisfy low resistance. Korean patent No. 2005-0061285 discloses a manufacturing method of metal pattern by plating desirable metals after forming potential patterns using photocatalytic compounds on the substrates, but it also has disadvantages that the activation time of potential patterns are short and there are high defective proportions due to the continuous process.
Japanese Laid-Open Patent Publication No. 2003-502507 discloses a fabrication method of metal patterns by electroless plating after forming catalytic pattern layers, which are pressed through a micro stamp on the surface of the substrates, but it is hard to form uniform lines.
US patent No. 2004-043691 discloses a direct formation method of metal ink patterns through inkjet printing, but it is hard to form metal patterns with high resolution and low resistance and its manufacturing speed is slow.
Japanese Patent Publication No. 2002-511643 discloses a plating method of printing patterns on the substrates. The above patterns are printed using polymer materials having conductive particles, which is well-known art. Yet, it is hard to print thin and uniform patterns with existing technology and the said patent does not provide specific solutions for pattern printing methods.